MACROMODELING LIBRARY TASK GROUP FILES

The Macromodeling Library Task Group exists to create and promote tool-independent model
collections consisting of modular equivalent functions and operators under both SPICE and
the mixed-signal languages Verilog-AMS and VHDL-AMS.  A Macromodeling Library allows tools
that support Verilog- and VHDL-AMS to directly use Library -AMS code; tools which do not
support the -AMS languages may use code defined in SPICE, with guaranteed equivalency. 

The chair of the TaskG Group is Arpad Muranyi (arpad.muranyi@intel.com).  To join the
discussions, visit http://www.freelists.org/archives/ibis-macro/.

Files and directories:

  /minutes                  - minutes of Task Group meetings

  arpadmuranyi.zip                 - Test file collection from A. Muranyi (7/26/2005)
  dac2005.zip                      - Introductory presentation on Task Group objectives, DAC IBIS Summit (7/26/2005)
  donaldtelian.zip                 - Example models and feature support list from Don Telian (7/26/2005)
  dons_feature_list.txt            - Macromodel building block list from Don Telian (9/6/2005)
  ibis_2010_examples.dml           - Macromodel examples in Cadence DML format (8/2/2005)
  ibis_macro_library_2005_08_16.va - Verilog-A Macromodel Library (8/25/2005)
  ibis_macro_library_2005_08_23.va - Verilog-A Macromodel Library (8/25/2005)
  ibis_macro_library_2005_08_30.va - Verilog-A Macromodel Library (9/6/2005)
  ibis_macro_library_2005_08_31.va - Verliog-A Macromodel Libarary (9/6/2005)
  mikelabonte.zip                  - Macromodel hierarchy and example Verilog-A file by M. Labonte (7/26/2005)
  predeemphasis.zip                - Verilog-A model for Pre-emphasis by A. Muranyi (7/26/2005)
  verilog_ams_lrm_2.2.pdf          - Verilog-AMS Language Reference Manual, rev. 2.2 (7/26/2005)

Last Updated: September 30, 2005